The present disclosure relates to integrated circuit (IC) structures in complementary metal oxide semiconductor (CMOS) circuits. More particularly, the present disclosure relates to on-chip decoupling capacitor structures having trench decoupling capacitors integrated with a planar decoupling capacitors.
One goal for semiconductor designers is to design highly reliable, super high performance CMOS circuits with ever increasing functionality requirements, while consuming the lowest possible power. This becomes more important for low power battery operated devices where battery-operating lifetime is crucial.
In this mode of operation, circuit designers face a number of challenges to insure high signal integrity within the chip and the semiconductor package. Simultaneous switching through the input and output (I/O) pins give to current “noise” spike within a specified time, severely degrading the signal integrity. The signal integrity is jeopardized mainly by the “noise” on the power and ground planes due to the capacitance coupling between power and signal lines.
To insure the system reliability against such deleterious effects, decoupling capacitors, known as DECAPS, are added to the power and ground planes to provide an AC ground for the noise and provide a stable DC voltage.
One currently methodology for embedding a DECAP on a microprocessor is to use a planar gate oxide in conjunction with available structures in the semiconductor process flow. For example, planar gate oxides have been used to form N-type decoupling capacitors, known as NCAPS, and P-type decoupling capacitors, known as PCAPS, metal-oxide-silicon capacitors (MOSCAP), and others. The capacitance of such planar DECAPS strongly depends on the thickness of the gate oxide. Thus, planar DECAPS are formed on the surface of the device. Unfortunately, current planar DECAPS offer higher leakage current and lower capacitance density, leading to larger chip sizes, lower performance, and higher cost.
Another current methodology for embedding a DECAP on a microprocessor is to form a trench-type capacitor that is made directly in the silicon wafer and the sidewalls of the trench are used for the capacitor dielectric. Such trench-type capacitors offer higher capacitance densities over the planar capacitors and lower leakage current. Unfortunately, the area density of deep trench DECAPS is limited by the thickness of the substrate.
However, there is a continuing need in the integrated circuit industry for increased decoupling capacitance beyond that currently available.